BEGIN:VCALENDAR
VERSION:2.0
PRODID:-//HiPEDS – EPSRC Centre for Doctoral Training - ECPv6.15.11//NONSGML v1.0//EN
CALSCALE:GREGORIAN
METHOD:PUBLISH
X-ORIGINAL-URL:https://wp.doc.ic.ac.uk/hipeds
X-WR-CALDESC:Events for HiPEDS – EPSRC Centre for Doctoral Training
REFRESH-INTERVAL;VALUE=DURATION:PT1H
X-Robots-Tag:noindex
X-PUBLISHED-TTL:PT1H
BEGIN:VTIMEZONE
TZID:UTC
BEGIN:STANDARD
TZOFFSETFROM:+0000
TZOFFSETTO:+0000
TZNAME:UTC
DTSTART:20180101T000000
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=UTC:20190329T120000
DTEND;TZID=UTC:20190329T130000
DTSTAMP:20260418T065455
CREATED:20190321T164209Z
LAST-MODIFIED:20190321T164209Z
UID:2022-1553860800-1553864400@wp.doc.ic.ac.uk
SUMMARY:HiPEDS seminar: Certifying Multicore Timing Analysis for Real-Time Systems
DESCRIPTION:Title: Certifying Multicore Timing Analysis for Real-Time Systems \nSpeaker: Dr Guillem Bernat\, Rapita Systems \nAbstract: The potential for increased performance by using multicore processors is not in question. Their use offers a solution to break the memory\, power and instruction level parallelism (ILP) walls that prevent single-core platforms from meeting the increasing demands of modern embedded avionics software. \nIn the aerospace industry\, adherence to safety guidelines such as DO-178B/C is expected. To adhere\, applicants must show that software always completes operations within a specified time (commonly called the worst-case execution time or WCET). Approaches to calculate WCET on single-core systems are not directly transferrable to multicore systems\, however\, requiring the use of novel technologies. \nIn this presentation\, we demonstrate a practical approach for calculating WCET on multicore platforms that is applicable to the DO-178B/C environment. This involves using high-quality timing analysis tools to understand the timing behaviour of the CPU by using “micro benchmarks”\, and assessing the impact of interference from multicore resource contention by applying carefully-constructed “adversaries” that force high levels of contention. \nBiography: Dr Guillem Bernat is the CEO and a founder of Rapita Systems. He received his PhD in Computer Science from the Universitat de les Illes Balears in Spain\, in 1998 and then took a lecturing position at the Real-Time Systems Group at the University of York in the UK. In 2004 he founded Rapita Systems to commercialise technology for measurement based worst-case execution time analysis technology. Rapita Systems has grown to provide a set of software verification tools for safety critical systems including timing analysis\, WCET analysis and structural code coverage to satisfy DO-178B/C and ISO26262 objectives. Dr. Bernat has more than 70 published papers in international conferences and Journals\, has lectured extensively in real-time systems and is a frequent speaker at international conferences.
URL:https://wp.doc.ic.ac.uk/hipeds/event/hipeds-seminar-certifying-multicore-timing-analysis-for-real-time-systems/
LOCATION:Huxley 217/218\, 180 Queens Gate\, Imperial College London\, London\, SW7 2AZ\, United Kingdom
END:VEVENT
END:VCALENDAR