Seminar: Automatically Comparing Memory Consistency Models
2016-10-26 12:00 - 13:00 UTC | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
S-REPLS Seminar Slides
Speaker name: Dr. John Wickerson
Abstract
A memory consistency model (MCM) is the part of a programming language or computer architecture specification that defines which values can legally be read when a thread in a concurrent program reads from a shared memory location. Because MCMs have to take into account various optimisations employed by modern architectures (such as store buffering and instruction reordering) and compilers (such as constant propagation), they often end up being complex and counterintuitive, which makes them challenging to design and to understand.

In this work, we identify four important tasks involved in designing and understanding MCMs: generating conformance tests, distinguishing two MCMs, checking compiler optimisations, and checking compiler mappings. We show that all four tasks can be cast as instances of a general constraint-satisfaction problem to which the solution is either a program or a pair of programs. We further show that although these constraints aren’t tractable for automatic solvers when phrased over programs directly, we can solve analogous constraints over programexecutions, and then reconstruct programs that satisfy the original constraints.

We illustrate our technique, which is implemented in the Alloy modelling framework, on a range of software- and architecture-level MCMs, both axiomatically and operationally defined. First, we automatically recreate – often in a simpler form – several known results, including: distinctions between several variants of the C/C++ MCM; a failure of the ‘SC-DRF guarantee’ in an early C++ draft; that x86 is ‘multi-copy atomic’ and Power is not; bugs in common C/C++ compiler optimisations; and bugs in compiler mappings from OpenCL to AMD-style and NVIDIA GPUs. Second, we use our technique to develop and validate a stronger MCM for NVIDIA GPUs that supports a natural mapping from OpenCL.

This is joint work with Mark Batty (U Kent), Tyler Sorensen (Imperial) and George A. Constantinides (Imperial).

Seminar: Deep Learning Financial Market Data
2016-12-12 12:00 - 13:00 | Huxley 145, Imperial College London, SW7 2AZ, United Kingdom
Speaker: Steven Hutt
Seminar title: Deep Learning Financial Market Data
Abstract: An introduction to learning patterns in financial market data
Slides

Seminar - Predicting User Demographics in Social Networks
2017-02-22 12:00 - 14:00 | 340 Huxley
Speaker name: Nikolaos Aletras
Abstract: Automatically inferring user demographics in social networks is useful for both social science research and a range of downstream applications in marketing and politics. Our main hypothesis is that language use in social networks is indicative of user attributes. This talk presents recent work on inferring a new set of socioeconomic attributes, i.e. occupational class, income and socioeconomic class. We define a predictive task for each attribute where user-generated content is utilised to train supervised non-linear methods for classification and regression, i.e. Gaussian Processes. We show that our models achieve strong predictive accuracy in all of the three demographics while our analysis sheds light to factors that differentiate users between occupations, income level and socioeconomic classes.
Bio: Dr. Nikolaos Aletras is an Applied Scientist at Amazon working in the Machine Learning Core team. Previously, I worked as a Research Associate at the Department of Computer Science at UCL, Media Futures Group and I completed a PhD in NLP at the Department of Computer Science of the University of Sheffield.

Predicting User Demographics in Social Networks
2017-02-22 12:00 - 14:00 | 340 Huxley
Speaker name: Nikolaos Aletras
Automatically inferring user demographics in social networks is useful for both social science research and a range of downstream applications in marketing and politics. Our main hypothesis is that language use in social networks is indicative of user attributes. This talk presents recent work on inferring a new set of socioeconomic attributes, i.e. occupational class, income and socioeconomic class. We define a predictive task for each attribute where user-generated content is utilised to train supervised non-linear methods for classification and regression, i.e. Gaussian Processes. We show that our models achieve strong predictive accuracy in all of the three demographics while our analysis sheds light to factors that differentiate users between occupations, income level and socioeconomic classes.
Dr. Nikolaos Aletras is an Applied Scientist at Amazon working in the Machine Learning Core team. Previously, I worked as a Research Associate at the Department of Computer Science at UCL, Media Futures Group and I completed a PhD in NLP at the Department of Computer Science of the University of Sheffield.

Seminar: Challenges in Operational Technology for the Process Industry
2017-03-09 15:00 - 16:00 | 611 (Gabor Seminar Room), EEE Building
Abstract
The following main challenges at the interface of automation technology, process technology and information technology will be discussed:

Models within the life-cycle
Vertical integration from ERP (Enterprise Resource Planning) to actuator and vice versa
Horizontal integration requirements for highly reliable solutions
Human Machine Integration

For all of these challenges the state-of-the-art and current BASF approaches will be presented.
The goal of the seminar is to create awareness for practical problems in the process industry and stimulate further discussions, as well as how the scientific community can contribute to develop improved solutions for these existing and upcoming challenges.
Short Bio
Dr Birk obtained his PhD on Computer-aided analysis and design of nonlinear observers in 1992 from the University of Stuttgart. He joined BASF afterwards, and has had several roles in the company ranging through Engineer in Advanced process Control to Senior Manager of Automation Technology to his current position as Vice President, Executive Expert of Automation Technology. Dr Birk has lectured on several Master courses at the University of Stuttgart, on Process Control and Production IT, and recently on Operational technology.

Lecture/Workshop: Model Predictive Control from an Application Point of View in Process Industry
2017-03-10 11:00 - 13:00 | EEE 509A
The aim of this lecture is to provide an industrial perspective on Model Predictive Control with emphasis on:

Important practical requirements
Practice-proven solutions and approaches
Understanding the required efforts in terms of time and money
Differentiation between state of the art, state of science and vision (= inspirations for further developments)

Lecture outline

Motivation
Model Predictive Control for Continuous Plants
Nonlinear Model Predictive Control for Batch Plants
Real Time Optimization
Summary and Outlook

Short Bio
Dr Birk obtained his PhD on Computer-aided analysis and design of nonlinear observers in 1992 from the University of Stuttgart. He joined BASF afterwards, and has had several roles in the company ranging through Engineer in Advanced process Control to Senior Manager of Automation Technology to his current position as Vice President, Executive Expert of Automation Technology. Dr Birk has lectured on several Master courses at the University of Stuttgart, on Process Control and Production IT, and recently on Operational technology.

HiPEDS Seminar - Big graphs on big machines
2017-03-14 13:00 - 14:00 | Huxley Building 144, Imperial College London, London, SW7 2AZ, United Kingdom
Speaker: Dr. Tim Harris, Oracle Labs Cambridge
Seminar Title: HiPEDS Seminar – Big graphs on big machines
Abstract: Oracle’s largest SPARC M7 system provides 4096 hardware threads spread over 16 sockets in one cache-coherent address space. I will talk about our experience tuning graph analytics workloads to run well on this system, and how we went from an implementation that stopped scaling at around 200 threads to a version that provides super-linear speed-ups on PageRank and SSSP running on 1TB+ inputs over the full machine. I will focus on the interactions between the threads and the memory system, and the lessons we learned in terms of how to allocate memory and distribute work on these large NUMA systems.
Bio: Tim Harris leads the Oracle Labs group in Cambridge, UK. His research interests span multiple layers of the stack, including parallel programming, VMM / OS / runtime-system interaction, and opportunities for specialized architecture support for particular workloads. He has also worked on the implementation of software transactional memory for multi-core computers, and the design of programming language features based on it. He is a co-author of the Morgan Claypool book Transactional Memory. Tim has a BA and PhD in computer science from Cambridge University Computer Laboratory. He was on the faculty at the Computer Laboratory from 2000-2004 where he led the department’s research on concurrent data structures and contributed to the Xen virtual machine monitor project. He was at Microsoft Research from 2004, and then joined Oracle Labs in 2012.

Slides

Data Co-Management with Modern Hardware
2017-05-18 12:00 - 14:00 | 611 (Gabor Seminar Room), EEE Building
Upcoming lecture by Raja Appuswamy, Postdoctoral Researcger in the DIAS lab at EPFL, on data management systems
Abstract
The design of data management systems has always been driven based on two aspects, namely, underlying hardware and applications requirements. The past few years have, however, witnessed dramatic changes in both these aspects.
On the hardware front, computer architecture is in a phase of constant change resulting in growing heterogeneity in the design of processors, memory, interconnects, and storage. With the wide-spread adoption of cloud computing, cloud providers have started deploying customized hardware in datacenters to balance price-power-performance trifecta, fueling this trend further. On the application front, many organizations increasingly require fast analytics on fresh transactional data to derive timely insights. The workload generated by the ensuing new breed of applications, also referred as “analytics 3.0” or “operational analytics”, is also heterogeneous in nature, as it blends transactional and analytical queries into a single stream.
In this talk, I will present two projects I started in the DIAS laboratory with the focus of building data management systems that can embrace and exploit hardware and workload heterogeneity. First, I will present Skipper, an end-to-end query execution framework that enables cheap data analytics directly over cold storage devices. Then, I will present Caldera, a new Hybrid Transactional and Analytical Processing (HTAP) engine that uses heterogeneous processors (CPUs and GPGPUs) in a synergistic fashion for supporting high-throughput transaction workloads and real-time analytical workloads without any compromises. In presenting these systems, I will both highlight the inability of current system designs to deal with emerging hardware and the potential of hardware–software codesign techniques to bring about substantial improvement in price, performance, or power consumption.
Speaker bio
Raja Appuswamy is currently working as a Postdoctoral Researcher in the DIAS lab headed by Prof. Anastasia Ailamaki at EPFL. Previously, he worked as a Visiting Researcher in the Systems and Networking group at Microsoft Research, Cambridge, and as a Software Development Engineer in the Windows 7 kernel team at Microsoft, Redmond.
He received his Ph.D in Computer Science from the Vrije Universiteit, Amsterdam, where he worked under the guidance of Prof. Andrew S. Tanenbaum on designing and implementing a new storage stack for the MINIX 3 microkernel operating system. He also holds dual Masters degrees in Computer Science and Agricultural Engineering from the University of Florida.

HiPEDS Seminar: Web Data Extraction: A Crash Course
2017-08-23 12:00 - 13:00 | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
HiPEDS CDT Seminar Series with Giorgio Orsi, Senior Research Scientist at Meltwater.

Abstract: Data acquisition plays an important role in modern organisations and is a strategic business process for data-driven companies such as insurers, retailers, and search engines. Data acquisition processes range from manual data collection and purchase, to cheaper but often technically challenging methods such as automated collection and crowdsourcing. The abundance of web data has made web scraping (also known as web data extraction or web wrapping) an essential tool in data acquisition processes. A wrapper is a program that turns web content into structured data using techniques ranging from visual analysis of the rendered page to DOM tree mining. Web scraping is often the only viable data collection method for websites, in particular when no API is available. Although web scraping typically relies on inducing a wrapper for every source, a number of semi- or fully automated techniques for web scraping have emerged. These recent advances have finally allowed for accurate and fully automated wrapper induction at the scale of hundreds of thousands of sources. They have also contributed to revitalised the area, as evident from a growing number of web scraping startups, e.g., Import.io, DiffBot, ScrapingHub, and Wrapidity.

This lecture is a crash course in Web Scraping. We will start with an overview of the available techniques and technologies, discussing when and where they are appropriate. We will then introduce the Open Source OXPath language for declarative web scraping.

Bio: Giorgio Orsi is a Senior Research Scientist at Meltwater and an Honorary Researcher at the School of Computer Science of the University of Birmingham. His research deals with the algorithmic aspects of large-scale data processing and with the logical foundations of information integration and knowledge representation. Giorgio is a co-investigator of the EPSRC Programme Grant VADA (Value Added Data Systems) and a co-founder of Wrapidity, an Oxford University startup, that was recently acquired by Meltwater to boost collection of outside data using AI.

HiPEDS Seminar: Database storage tiering, fast and slow
2017-10-06 12:00 - 13:00 | Huxley 139
Abstract:
In 1987, Jim Gray and Gianfranco Putzolu introduced the five-minute rule for trading memory to reduce disk I/O using the then-current price-performance characteristics of DRAM and Hard Disk Drives (HDD). Since then, the five-minute rule has gained wide-spread acceptance as an important rule-of-thumb in data engineering. In the first part of this talk, we will revisit the five-minute rule three decades since its introduction and use it to identify impending changes in today’s multi-tier storage hierarchy given recent trends in the storage hardware landscape.
In the second part of the talk, we will use insights from the five-minute rule to investigate the impact of merging the erstwhile-separate capacity and archival tiers into a single cold storage tier that is based on new Cold Storage Devices (CSD). We will see that despite its ability to reduce TCO, cold storage tier cannot be realized in practice today as current database systems will suffer from crippling performance problems if CSD are used as a replacement for HDD. Then, I will present Skipper, an end-to-end query execution framework that substantially reduces the cost of data analytics by enabling query execution directly over CSD.
Bio:
Raja Appuswamy is currently working as a Postdoctoral Researcher in the DIAS lab headed by Prof. Anastasia Ailamaki at EPFL. Previously, he worked as a Visiting Researcher in the Systems and Networking group at Microsoft Research, Cambridge, and as a Software Development Engineer in the Windows 7 kernel team at Microsoft, Redmond.
He received his PhD in Computer Science from the Vrije Universiteit, Amsterdam, where he worked under the guidance of Prof. Andrew S. Tanenbaum on designing and implementing a new storage stack for the MINIX 3 microkernel operating system. He also holds dual Masters degrees in Computer Science and Agricultural Engineering from the University of Florida.

HiPEDS Seminar: How can you trust formally verified software?
2017-11-06 12:00 - 13:00 | 611 (Gabor Seminar Room), EEE Building
Abstract:
Formal verification of software has finally started to become viable: we have examples of formally verified microkernels, realistic compilers, hypervisors etc. These are huge achievements and we can expect to see even more impressive results in the future but the correctness proofs depend on a number of assumptions about the Trusted Computing Base that the software depends on. Two key questions to ask are: Are the specifications of the Trusted Computing Base correct? And do the implementations match the specifications? I will explore the philosophical challenges and practical steps you can take in answering that question for one of the major dependencies: the hardware your software runs on. I will describe the combination of formal verification and testing that ARM uses to verify the processor specification and I will talk about our current challenge: getting the specification down to zero bugs while the architecture continues to evolve.
Bio:
Alastair Reid is a Senior Principal Research Engineer at ARM Ltd. His current research focus is on formalizing the ARM architecture specifications and finding ways that those specifications can be used to make hardware and software better. He has 17 granted patents in Computer Architecture and has published over a dozen research papers in Formal Verification, Software Defined Radio, Operating Systems, and Lazy Functional Programming. Before ARM, he worked/studied at University of Utah, Yale University, University of Glasgow and the University of Strathclyde. In his spare time, he builds his own keyboards and enjoys trashing his body in cyclocross races. You can find him at https://alastairreid.github.io and at @alastair_d_reid.

HiPEDS Seminar: Distributed Private Data Collection at Scale
2018-01-19 12:00 - 13:00 | Huxley Building Room 218, Imperial College London, London, SW7 2AZ, United Kingdom
Abstract:
Large technology companies rely on collecting data from their users to understand their interests, and better customize the company’s products. Increasingly, this must be done while preserving individual users’ privacy. Recently, techniques based on radomization and data sketching have been adopted to provide data collection protocols which optimize the privacy accuracy trade-off. In this talk, I’ll discuss methods deployed by Google and Apple to collect frequency information, and our recent work to monitor information on correlations in the data.
Bio:
Graham Cormode a Professor in Computer Science at the University of Warwick in the UK, where he work on research topics in data management, privacy and big data analysis. Previously, he was a principal member of technical staff at AT&T Labs-Research. He is a University Liaison Director at the Alan Turing Institute, and in 2017 he was the co-recipient of Adams Prize for Mathematics for his work on Statistical Analysis of Big Data.

HiPEDS Seminar: Big Data and the Cloud: Implications for Structured Data Management
2018-03-16 14:00 - 15:00 | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
Abstract: I will present an overview of some of the open challenges and opportunities for structured data management that are especially relevant for today’s world of Big Data and the Cloud. In the second half of the talk, I will discuss in depth one of the opportunities – approximate query processing – and reflect on why this technology is not mainstream in today’s data platforms.
Bio: Surajit Chaudhuri is a Distinguished Scientist at Microsoft Research and leads the Data Management, Exploration and Mining group. He also works closely with Microsoft’s Cloud and Enterprise Division. Surajit’s current areas of interest are Big Data platforms, self-manageability, and cloud database services. Working with his colleagues in Microsoft Research, he helped incorporate the Database Engine Tuning Advisor and Data Cleaning technology in Microsoft SQL Server. Surajit is an ACM Fellow, a recipient of the ACM SIGMOD Edgar F. Codd Innovations Award, ACM SIGMOD Contributions Award, a VLDB 10-year Best Paper Award, and an IEEE Data Engineering Influential Paper Award.

HiPEDS Seminar: What's new in TensorFlow? Updates from the Developer Summit.
2018-04-12 16:00 - 17:00 | Huxley 140
Abstract: Many new and exciting things are coming for TensorFlow, to be announced at the Developer Summit on 3/30 in Mountain View. Since this event will have just finished by the time I make it out the UK, I thought it’d be helpful to give a quick summary / overview of these new features and opportunities, then dive a little deeper into the topics that are most relevant to you. My focus is on usability, in particular – I’m excited about Eager Execution and Keras. I can also go a little deeper (no pun) into important work being done on DeepLearn.js, which may be valuable for researchers to create “instant demos” of their models, running in a webpage, with no installation necessary for users.
Length: About 45 mins, or less. Happy to do 1:1s after to go deeper into topics of interest.
Short bio: Josh Gordon works on the TensorFlow team at Google, and teaches Deep Learning at Pace University. He has over a decade of machine learning experience to share. You can find him on YouTube and Twitter.

HiPEDS Seminar: Probabilistic models and principled decision making @ PROWLER.io
2018-05-30 12:00 - 13:00 | RSM G41, Imperial College London, London, SW7 2AZ, United Kingdom
Abstract:
What use is machine learning unless we can turn predictions into decisions? In this talk I’ll explain how this idea motivates our strategy at PROWLER.io. I’ll explain how different research teams at the company are attacking different parts of decision theory, and focus on outputs from the probabilistic modelling team. I’ll show how probabilistic models are used for forecasting in smart cities, and examine some of the machine learning advances we’ve made to achieve this.
Short Bio:
James Hensman is the head of probabilistic modelling at PROWLER.io. He was previously a Lecturer at Lancaster University, where he held a MRC fellowship in Biostatistics. He obtained his PhD from Sheffield University, where he studied engineering. His interests are in statistical machine learning including Gaussian process models; he co-founded the GPy and GPflow packages.

HiPEDS Seminar: Building Computer Vision Systems That Really Work
2018-11-02 14:00 - 15:00 | Huxley 342
Title: Building Computer Vision Systems That Really Work
Speaker: Andrew Fitzgibbon, Microsoft [<– note not MS Research]
Andrew Fitzgibbon has been shipping advanced computer vision systems for twenty years. In 1999, prize-winning research from Oxford University was spun out to become the Emmy-award-winning camera tracker “boujou”, which has been used to insert computer graphics into live-action footage in pretty much every movie made since its release, from the “Harry Potter” series to “Bridget Jones’s Diary”. In 2007, he was part of the team that delivered human body tracking in Kinect for Xbox 360, and in 2015 he moved from Microsoft Research to the Windows division to work on Microsoft’s HoloLens, an AR headset brimming with cutting-edge computer vision technology. In all of these projects, the academic state of the art has had to be leapfrogged in accuracy and efficiency, sometimes by several orders of magnitude. Sometimes that’s just raw engineering, sometimes it means completely new ways of looking at the research. If he had to nominate one key to success, it’s a focus on, well, everything: from cache misses to end-to-end experience, and on always being willing to change one’s mind.
Biography: Fitzgibbon is a partner scientist at Microsoft in Cambridge, UK. He has published numerous highly-cited papers, and received many awards for his work, including ten “best paper” prizes at various venues, the Silver medal of the Royal Academy of Engineering, and the BCS Roger Needham award. He is a fellow of the Royal Academy of Engineering, the British Computer Society, and the International Association for Pattern Recognition. He studied at University College, Cork, and then did a Masters at Heriot-Watt University, before taking up an RSE job at the University of Edinburgh, which eventually morphed into a PhD. He moved to Oxford in 1996 and drove large software projects such as the VXL project, and then spent several years as a Royal Society University Research Fellow before joining Microsoft in 2005. He loves programming, particularly in C++, and his recent work has included new numerical algorithms for Eigen, and compilation of F# to a non-garbage-collected runtime.
https://www.microsoft.com/en-us/research/people/awf/

An IP provider’s perspective on functional safety
2018-11-26 16:00 - 17:00 | EEE Level 9 Seminar Room
Title: An IP provider’s perspective on functional safety
Speaker: Pete Harrod, Director of Functional Safety at Arm, Cambridge. Royal Academy of Engineering Visiting Professor in Dependable Embedded Computing, Imperial
In this talk, Pete will briefly tell you something about himself, his time at Arm and what he does there now – and introduce his role as a part-time Visiting Professor and what he hopes to achieve in the 3 years that he will be doing this. But the focus of the talk will be on how an IP provider such as Arm can develop products that can be used in applications where safety is a key concern. By using ‘Connected and Highly Automated Vehicles’ (so-called self-driving cars) as an example, he’ll explain how the design and verification process needs to proceed to meet the requirements of safety standards and discuss the types of faults that can occur and how they need to be handled. By describing one of the latest Arm CPUs that support functional safety, he’ll show what can be achieved at the IP level. He’ll conclude with a look at future challenges and areas that are ripe for collaborative research.
Biography: Pete is one of the 12 founding engineers of Arm and is still there 28 years later, having taken on a number of roles in design, test, debug and now in functional safety. He is one of the UK experts on the working group that develops the ISO 26262 standard for automotive functional safety and is now contributing to a forthcoming standard on the ‘Safety of the Intended Functionality (SOTIF)’. He has a PhD from UMIST , is a Fellow of the IET and is on the steering committee of the European Test Symposium.

HiPEDS Seminar: Symbolic Repairs for GR(1) Specifications
2019-02-15 14:00 - 15:00 | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
Title: Symbolic Repairs for GR(1) Specifications
Speaker: Jan Oliver Ringert, Lecturer in Model-Based Software Development in the Department of Informatics at the University of Leicester
Abstract: Reactive synthesis is an automated procedure to obtain a correct-by-construction reactive system from a given specification. Examples include GR(1), an expressive assume-guarantee fragment of LTL, that enables efficient synthesis of the software controllers of robotic systems.
Unrealizability is a major challenge for synthesis. Some works attempt to help engineers deal with unrealizability by generating counter-strategies or computing an unrealizable core. Other works propose to repair the unrealizable specification by suggesting repairs in the form of automatically generated assumptions.
We present two novel symbolic algorithms for repairing unrealizable GR(1) specifications. The first algorithm infers new assumptions based on the recently introduced JVTS. The second algorithm infers new assumptions directly from the specification. Both algorithms are sound. The first is incomplete but can be used to suggest many different repairs. The second is complete but suggests a single repair. Both are symbolic and therefore efficient.
Joint work with Shahar Maoz and Rafi Shalom within the ERC StG SYNTECH project that addresses challenges related to the change from writing code to writing specifications, and the development of tools to support a specification-centric rather than a code-centric development process. http://smlab.cs.tau.ac.il/syntech/
Biography: Jan Oliver Ringert joined the Department of Informatics of the University of Leicester, Leicester, UK in February 2018 as a Lecturer in Model-Based Software Development. Previously, he was a PostDoc in the Software Modeling group of Shahar Maoz at the School of Computer Science, Tel Aviv University, Israel (12/2013-01/2018). Before, he worked in the Software Engineering group of Bernhard Rumpe at RWTH Aachen University, Germany (10/2008-11/2013). He received his Computer Science diploma (Dipl.-Inform.) from TU Braunschweig, Germany (2003-2008).
His research interests include model-based software engineering with a focus on software evolution and the software engineering aspects of synthesis of reactive systems.

HiPEDS seminar: Certifying Multicore Timing Analysis for Real-Time Systems
2019-03-29 12:00 - 13:00 | Huxley 217/218, 180 Queens Gate, Imperial College London, London, SW7 2AZ, United Kingdom
Title: Certifying Multicore Timing Analysis for Real-Time Systems
Speaker: Dr Guillem Bernat, Rapita Systems
Abstract: The potential for increased performance by using multicore processors is not in question. Their use offers a solution to break the memory, power and instruction level parallelism (ILP) walls that prevent single-core platforms from meeting the increasing demands of modern embedded avionics software.
In the aerospace industry, adherence to safety guidelines such as DO-178B/C is expected. To adhere, applicants must show that software always completes operations within a specified time (commonly called the worst-case execution time or WCET). Approaches to calculate WCET on single-core systems are not directly transferrable to multicore systems, however, requiring the use of novel technologies.
In this presentation, we demonstrate a practical approach for calculating WCET on multicore platforms that is applicable to the DO-178B/C environment. This involves using high-quality timing analysis tools to understand the timing behaviour of the CPU by using “micro benchmarks”, and assessing the impact of interference from multicore resource contention by applying carefully-constructed “adversaries” that force high levels of contention.
Biography: Dr Guillem Bernat is the CEO and a founder of Rapita Systems. He received his PhD in Computer Science from the Universitat de les Illes Balears in Spain, in 1998 and then took a lecturing position at the Real-Time Systems Group at the University of York in the UK. In 2004 he founded Rapita Systems to commercialise technology for measurement based worst-case execution time analysis technology. Rapita Systems has grown to provide a set of software verification tools for safety critical systems including timing analysis, WCET analysis and structural code coverage to satisfy DO-178B/C and ISO26262 objectives. Dr. Bernat has more than 70 published papers in international conferences and Journals, has lectured extensively in real-time systems and is a frequent speaker at international conferences.

Seminar: Modernising Asychronous C++
2019-06-10 15:00 - 16:00 | Huxley Building 144, Imperial College London, London, SW7 2AZ, United Kingdom
Title: Modernising Asychronous C++
Speaker: Lee Howes, Facebook
Abstract: In C++11, C++ finally officially discovered concurrency. The advent of an official memory model and atomic operations made possible what had earlier relied on implementation-defined behaviour. In C++17, C++ acquired parallel algorithms – a very basic subset of what OpenMP offers, but a start towards parallelism in the C++ standard. C++20 will get coroutines – finally in-language async/await syntax. The last few years has been a long mission in trying to define concurrency abstractions and a wider set of parallel algorithms. In this talk I’ll give a little history, some idea of why I and why Facebook cares about moving C++ into the future, and some idea of where we may take it.
Biography: Lee Howes did his undergraduate degree in DoC, and a PhD with Professor Paul Kelly in programming models for parallel computing. He spent 6 years working on the boundary of hardware and software, defining software acceleration standards in the Khronos Group and HSA Foundation, at various times editing the OpenCL and SYCL specifications and defining memory consistency models for GPUs and building cache architecture. He currently leads Facebook’s C++ language and libraries team, helping Facebook advance a vision of native compilation for large scale distributed, heterogeneous systems.
