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X-WR-CALNAME:HiPEDS – EPSRC Centre for Doctoral Training
X-ORIGINAL-URL:https://wp.doc.ic.ac.uk/hipeds
X-WR-CALDESC:Events for HiPEDS – EPSRC Centre for Doctoral Training
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TZID:UTC
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DTSTART:20180101T000000
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BEGIN:VEVENT
DTSTART;TZID=UTC:20190329T120000
DTEND;TZID=UTC:20190329T130000
DTSTAMP:20260419T032622
CREATED:20190321T164209Z
LAST-MODIFIED:20190321T164209Z
UID:2022-1553860800-1553864400@wp.doc.ic.ac.uk
SUMMARY:HiPEDS seminar: Certifying Multicore Timing Analysis for Real-Time Systems
DESCRIPTION:Title: Certifying Multicore Timing Analysis for Real-Time Systems \nSpeaker: Dr Guillem Bernat\, Rapita Systems \nAbstract: The potential for increased performance by using multicore processors is not in question. Their use offers a solution to break the memory\, power and instruction level parallelism (ILP) walls that prevent single-core platforms from meeting the increasing demands of modern embedded avionics software. \nIn the aerospace industry\, adherence to safety guidelines such as DO-178B/C is expected. To adhere\, applicants must show that software always completes operations within a specified time (commonly called the worst-case execution time or WCET). Approaches to calculate WCET on single-core systems are not directly transferrable to multicore systems\, however\, requiring the use of novel technologies. \nIn this presentation\, we demonstrate a practical approach for calculating WCET on multicore platforms that is applicable to the DO-178B/C environment. This involves using high-quality timing analysis tools to understand the timing behaviour of the CPU by using “micro benchmarks”\, and assessing the impact of interference from multicore resource contention by applying carefully-constructed “adversaries” that force high levels of contention. \nBiography: Dr Guillem Bernat is the CEO and a founder of Rapita Systems. He received his PhD in Computer Science from the Universitat de les Illes Balears in Spain\, in 1998 and then took a lecturing position at the Real-Time Systems Group at the University of York in the UK. In 2004 he founded Rapita Systems to commercialise technology for measurement based worst-case execution time analysis technology. Rapita Systems has grown to provide a set of software verification tools for safety critical systems including timing analysis\, WCET analysis and structural code coverage to satisfy DO-178B/C and ISO26262 objectives. Dr. Bernat has more than 70 published papers in international conferences and Journals\, has lectured extensively in real-time systems and is a frequent speaker at international conferences.
URL:https://wp.doc.ic.ac.uk/hipeds/event/hipeds-seminar-certifying-multicore-timing-analysis-for-real-time-systems/
LOCATION:Huxley 217/218\, 180 Queens Gate\, Imperial College London\, London\, SW7 2AZ\, United Kingdom
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BEGIN:VEVENT
DTSTART;TZID=UTC:20190610T150000
DTEND;TZID=UTC:20190610T160000
DTSTAMP:20260419T032622
CREATED:20190606T123720Z
LAST-MODIFIED:20190606T123720Z
UID:2048-1560178800-1560182400@wp.doc.ic.ac.uk
SUMMARY:Seminar: Modernising Asychronous C++
DESCRIPTION:Title: Modernising Asychronous C++ \nSpeaker: Lee Howes\, Facebook \nAbstract: In C++11\, C++ finally officially discovered concurrency. The advent of an official memory model and atomic operations made possible what had earlier relied on implementation-defined behaviour. In C++17\, C++ acquired parallel algorithms – a very basic subset of what OpenMP offers\, but a start towards parallelism in the C++ standard. C++20 will get coroutines – finally in-language async/await syntax. The last few years has been a long mission in trying to define concurrency abstractions and a wider set of parallel algorithms. In this talk I’ll give a little history\, some idea of why I and why Facebook cares about moving C++ into the future\, and some idea of where we may take it. \nBiography: Lee Howes did his undergraduate degree in DoC\, and a PhD with Professor Paul Kelly in programming models for parallel computing. He spent 6 years working on the boundary of hardware and software\, defining software acceleration standards in the Khronos Group and HSA Foundation\, at various times editing the OpenCL and SYCL specifications and defining memory consistency models for GPUs and building cache architecture. He currently leads Facebook’s C++ language and libraries team\, helping Facebook advance a vision of native compilation for large scale distributed\, heterogeneous systems.
URL:https://wp.doc.ic.ac.uk/hipeds/event/seminar-modernising-asychronous-c/
LOCATION:Huxley Building 144\, Imperial College London\, London\, SW7 2AZ\, United Kingdom
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