HiPEDS – EPSRC Centre for Doctoral Training

Seminar: Deep Learning Financial Market Data
2016-12-12 12:00 - 13:00 UTC | Huxley 145, Imperial College London, SW7 2AZ, United Kingdom
Speaker: Steven Hutt
Seminar title: Deep Learning Financial Market Data
Abstract: An introduction to learning patterns in financial market data
Slides

Seminar: Automatically Comparing Memory Consistency Models
2016-10-26 12:00 - 13:00 | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
S-REPLS Seminar Slides
Speaker name: Dr. John Wickerson
Abstract
A memory consistency model (MCM) is the part of a programming language or computer architecture specification that defines which values can legally be read when a thread in a concurrent program reads from a shared memory location. Because MCMs have to take into account various optimisations employed by modern architectures (such as store buffering and instruction reordering) and compilers (such as constant propagation), they often end up being complex and counterintuitive, which makes them challenging to design and to understand.

In this work, we identify four important tasks involved in designing and understanding MCMs: generating conformance tests, distinguishing two MCMs, checking compiler optimisations, and checking compiler mappings. We show that all four tasks can be cast as instances of a general constraint-satisfaction problem to which the solution is either a program or a pair of programs. We further show that although these constraints aren’t tractable for automatic solvers when phrased over programs directly, we can solve analogous constraints over programexecutions, and then reconstruct programs that satisfy the original constraints.

We illustrate our technique, which is implemented in the Alloy modelling framework, on a range of software- and architecture-level MCMs, both axiomatically and operationally defined. First, we automatically recreate – often in a simpler form – several known results, including: distinctions between several variants of the C/C++ MCM; a failure of the ‘SC-DRF guarantee’ in an early C++ draft; that x86 is ‘multi-copy atomic’ and Power is not; bugs in common C/C++ compiler optimisations; and bugs in compiler mappings from OpenCL to AMD-style and NVIDIA GPUs. Second, we use our technique to develop and validate a stronger MCM for NVIDIA GPUs that supports a natural mapping from OpenCL.

This is joint work with Mark Batty (U Kent), Tyler Sorensen (Imperial) and George A. Constantinides (Imperial).

Engineering Lecture
2016-06-21 17:30 - 19:00 | Skempton 164, Skempton Building, Imperial College London, SW7 2AZ, United Kingdom
Dr Alastair Donaldson will be giving an exciting lecture on his research and its relevance for secondary school students. A booking form and further details will be available soon.

Seminar: Domain Specific Design Tools with application to Internet of Things
2016-06-17 12:00 - 13:00 | Huxley Building Room 218, Imperial College London, London, SW7 2AZ, United Kingdom
Speaker name: Dr. Benedict Gaster
Abstract
Internet of Things is an area of active interest, some people predicting a million unique devices in the next 5 years, all sharing a common lineage low-power and censoring the world. If this is really the case, then these devices must be designed and built by more than professional programmers and system architects! In this talk we introduce the notion of Domain Specific Design Tools (DSDT), that allow users of technology to design their own devices. In itself this is not a new idea, games engines are an excellent example of DSDTs, but IoT brings a new set of requirements that open challenges not addressed by existing tools and methods.
To build the DSDTs for future IoT applications, many not yet conceived, we present a Typescript and C++ framework that puts constraints on the development environment, such as listed memory and low-clock speeds, that rule of using many C++ features and instead propose a generalisation of C++ meta-programing as a library foundation for building DSDTs.

Seminar: Thinking Outside the (Network) Box
2016-05-17 11:00 - 12:00 | Huxley 145, Imperial College London, SW7 2AZ, United Kingdom
Speaker name: Dr. Paolo Costa
Abstract: Data centers are the infrastructure providing access to online services such as Amazon, Google Search, Facebook, and Office 365 for hundreds of millions of users around the world. They comprise hundreds of thousands of servers interconnected by a fast network fabric. The network is therefore a critical component of data centers and it is often cited as one of the main bottlenecks, affecting performance and costs.
Existing network deployments are heavily influenced by Internet-based technology. While this approach has served us well, it starts showing its limits. In this talk, I will review some of these shortcomings and discuss how the research undertaken in our group aims to address the challenges of future data centers through a deep rethinking of the way data center networks are built and operated.

Seminar: The SpiNNaker Project
2016-02-19 14:00 - 15:00 | Huxley Building 144, Imperial College London, London, SW7 2AZ, United Kingdom
Speaker name: Prof. Steve Furber
Abstract: The SpiNNaker project, now offered as one of two neuromorphic platforms supported by the European Union ICT Flagship Human Brain Project, is a digital many-core computer incorporating a million mobile phone processors optimised for real-time brain-modelling research applications. The design of the machine is very much influenced by the biological application it is intended to support, which has a lot to teach us about how we might build more efficient, fault-tolerant parallel computers in the future.
The SpiNNaker Project Seminar Slides

Monitoring the security health of a cloud server or smartphone
2016-01-25 17:00 - 18:00 | Huxley 145, Imperial College London, SW7 2AZ, United Kingdom
Speaker: Professor Ruby B. Lee
Abstract: Cloud computing provides computing resources to cloud customers on demand. It should also be able to provide different types and levels of security on demand, at different costs to the customers. But how does the customer know that he is getting the security services he paid for? Towards this end, a cloud provider needs to be able to monitor a server’s security health and see if this matches the security properties the customer requested. We defined CloudMonatt, an architecture that does this monitoring and attestation of security health. We discuss what security mechanisms are needed in each compute server and in the property-attestation server, how some security health properties can be inferred, and how scalable secure monitoring and property attestation can be achieved. What measurements can be easily collected from which security health properties can be inferred? Can existing performance monitoring or optimization features be used? Beyond the architectural framework, we would like to invite exploration of how machine learning can be used effectively to help determine various aspects of security health. Can these techniques also be used to detect security health in smartphones?
Speaker’s Bio: Ruby B. Lee is the Forrest G. Hamrick Professor in the Electrical Engineering department at Princeton University. Her research in security-aware computer architecture includes secure processors enabling fine-grained secure enclaves, secure caches resilient to side-channel attacks, software-hardware architectures for self-protecting data, cloud computing security, smart phone security and security verification. Prior to Princeton, Lee served as chief architect at Hewlett-Packard, contributing to numerous technical innovations in processor architecture, multimedia architecture and security architecture. She was a founding architect of HP’s PA-RISC architecture and instrumental in the initial design of several generations of PA-RISC processors for HP’s business and technical computers. She helped catalyze the widespread adoption of multimedia in commodity computers by pioneering subword-parallelism (SIMD) for multimedia acceleration in microprocessors, now supported in all major Instruction Set Architectures. She led the introduction of the first multimedia user interface in low-end products. She also co-led the 64-bit Intel-HP multimedia architecture team, and helped introduce SIMD and novel permutation instructions into Intel processors. Lee is an ACM Fellow and an IEEE Fellow, and holds over 120 U.S. and international patents. She received her undergraduate degree from Cornell in the college scholar program and her Ph.D. from Stanford University. Lee is a visiting professor at Imperial College.

Seminar: The past and future of Random Field Theory for neuroimaging inference
2016-01-11 16:00 - 17:00 | Huxley Building, Room 217/218, Imperial College London, London, SW7 2AZ, United Kingdom
Speaker name: Prof. Thomas E. Nichols
Abstract: A fundamental goal in “brain mapping” with functional Magnetic Resonance Imaging (fMRI) is localising the parts of the brain activated by a task. The standard tool for making this inference has been Random Field Theory (RFT), a collection of results for Gaussian Processes of the null statistic image (implemented in the two most widely used packages, SPM & FSL). RFT provides inference on individual voxels (voxel-wise) and sets of contiguous suprathreshold voxels (cluster-wise) while controlling the familywise error rate, the chance of one or more false positives over the brain. I will discuss how RFT methods have been used for the past 25 years, show some small-scale evaluations that pointed to problems with RFT when the degrees-of-freedom are low. I will then show results from a recent study based on the wealth of (1000’s of) publicly available resting-state fMRI datasets; these massive evaluations show that, even with n=20 or 40 subjects, RFT suffers from slightly conservative voxel-wise inferences and catastrophically liberal cluster-wise inferences. I will discuss the reasons for these failures of RFT and practical solutions going forward.
Seminar Slides from Prof. Nichols’ Talk

Seminar: Validating Optimizations of Concurrent C/C++ Programs
2015-12-01 11:00 - 12:00 | Huxley Building Room 218, Imperial College London, London, SW7 2AZ, United Kingdom
Speaker: Viktor Vafeiadis
The talk will discuss recent work on checking the correctness of LLVM compiler optimisations on C11 programs as far as concurrency is concerned. We have built a validator checks that optimisations performed by the compiler do not change memory accesses in ways disallowed by the C11 and/or LLVM memory models. Although the LLVM concurrency model has not yet fully been formalised, our experiments highlight an important difference between the C11 and LLVM memory models, which has led to some misunderstanding among compiler developers, which in turn led to concurrency-specific compilation errors. This is joint work with Soham Chakraborty.
Slides available here
